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| Presentation | 2017-01-24 16:55 FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.)  VLD2016-91 CPSY2016-127 RECONF2016-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper focuses on a method to detect outliers in streaming data, and proposes a fast FPGA implementation of outlier detection based on the Mahalanobis distance. The proposed circuit is fully pipelined, and in every clock cycle, a given sample data can be judged as an outlier or not. To calculate a mean vector and a covariance matrix for computing the Mahalanobis distance, a difference calculation method was proposed. Experimental evaluation shows that the proposed circuit is 37 times faster than the software implementation of the Mahalanobis distance-based outlier detection when the number of features of data is 4. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Outlier detection / Mahalanobis distance / FPGA / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 417, RECONF2016-72, pp. 141-146, Jan. 2017. | |
| Paper # | RECONF2016-72 | |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-91 CPSY2016-127 RECONF2016-72 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2017-01-23 - 2017-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2017-01-CPSY-RECONF-VLD-SLDM-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data |
| Sub Title (in English) | |
| Keyword(1) | Outlier detection |
| Keyword(2) | Mahalanobis distance |
| Keyword(3) | FPGA |
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| 1st Author's Name | Yuto Arai |
| 1st Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 2nd Author's Name | Shin'ichi Wakabayashi |
| 2nd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 3rd Author's Name | Shinobu Nagayama |
| 3rd Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
| 4th Author's Name | Masato Inagi |
| 4th Author's Affiliation | Hiroshima City University (Hiroshima City Univ.) |
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| Speaker | Author-1 |
| Date Time | 2017-01-24 16:55:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2016-91, CPSY2016-127, RECONF2016-72 |
| Volume (vol) | vol.116 |
| Number (no) | no.415(VLD), no.416(CPSY), no.417(RECONF) |
| Page | pp.141-146 |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
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