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Paper Abstract and Keywords
Presentation 2017-01-24 15:50
A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization
Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) For a pre-trained deep convolutional neural network (CNN) aim at an embedded system, a high-speed and a low power consumption are required. In the former of the CNN, it consists of convolutional layers, while in the latter, it consists of fully connection layers. In the convolutional layer, the multipliy accumulation operation is a bottleneck, while the fully connection layer, the memory access is a bottleneck. In this paper, we propose a neuron pruning technique which eliminates almost part of the weight memory. In that case, it is realized by an on-chip memory on the FPGA. Thus, it acheives a high speed memory access. In this paper, we propose a sequential-input parallel-output fully connection layer circuit. The experimental results showed that, by the neuron pruning, as for the fully connected layer on the VGG-11 CNN, the number of neurons was reduced by 76.4% with keeping the 99% accuracy. We implemented the fully connected layers on the Digilent Inc. NetFPGA-1G-CML FPGA board. Comparison with the CPU (ARM Cortex A15 processor) and the GPU (Jetson TK1 Kepler), as for a delay time, the FPGA was 219.0 times faster than the CPU and 12.5 times faster than the GPU. Also, a performance per power efficiency was 87.69 times better than CPU and 12.51 times better than GPU.
Keyword (in Japanese) (See Japanese page) 
(in English) Convolutinal Neural Network / FPGA / Pruning / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 417, RECONF2016-60, pp. 55-60, Jan. 2017.
Paper # RECONF2016-60 
Date of Issue 2017-01-16 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC  
Conference Date 2017-01-23 - 2017-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2017-01-CPSY-RECONF-VLD-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization 
Sub Title (in English)  
Keyword(1) Convolutinal Neural Network  
Keyword(2) FPGA  
Keyword(3) Pruning  
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1st Author's Name Tomoya Fujii  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Simpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Hiroki Nakahara  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
4th Author's Name Masato Motomura  
4th Author's Affiliation Hokkaido University (Hokkaido univ.)
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Speaker
Date Time 2017-01-24 15:50:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-VLD2016-79,IEICE-CPSY2016-115,IEICE-RECONF2016-60 
Volume (vol) IEICE-116 
Number (no) no.415(VLD), no.416(CPSY), no.417(RECONF) 
Page pp.55-60 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2017-01-16,IEICE-CPSY-2017-01-16,IEICE-RECONF-2017-01-16 


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