Paper Abstract and Keywords |
Presentation |
2017-01-24 14:20
Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.) VLD2016-87 CPSY2016-123 RECONF2016-68 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Such sensor network applicatio, which is one of core technologies in IoT, are requesting a change for consuming energy of processors installed as a platform. The requirement is processor operating with less consuming energy than permissible energy consumption in all states from the start to the end of operation after power-on. In this report, in order to follow the requirement prior to the start of operation for processor start up, we propose processors which are internally divided into modules registering predicted energy consumption to start up each module, distribute varying permissible energy consumption to those modules, and sequentially start up. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Processor / Energy consumption / Permissible energy consumption / Startup / Power on / Reset / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 417, RECONF2016-68, pp. 115-120, Jan. 2017. |
Paper # |
RECONF2016-68 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2016-87 CPSY2016-123 RECONF2016-68 |
Conference Information |
Committee |
CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
Conference Date |
2017-01-23 - 2017-01-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
RECONF |
Conference Code |
2017-01-CPSY-RECONF-VLD-SLDM-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption |
Sub Title (in English) |
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Keyword(1) |
Processor |
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Energy consumption |
Keyword(3) |
Permissible energy consumption |
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Startup |
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Power on |
Keyword(6) |
Reset |
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1st Author's Name |
Hiroaki Kaneko |
1st Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
2nd Author's Name |
Akinori Kanasugi |
2nd Author's Affiliation |
Tokyo Denki University (Tokyo Denki Univ.) |
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Speaker |
Author-1 |
Date Time |
2017-01-24 14:20:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2016-87, CPSY2016-123, RECONF2016-68 |
Volume (vol) |
vol.116 |
Number (no) |
no.415(VLD), no.416(CPSY), no.417(RECONF) |
Page |
pp.115-120 |
#Pages |
6 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
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