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| Presentation | 2017-01-23 15:20 Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)  VLD2016-75 CPSY2016-111 RECONF2016-56 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a multiple FPGA system using high speed optical serial interconnection for a inter-connection of FPGAs. In this paper, we can implement digital circuits on propose system as a ASIC emulator. Although traditional system which uses parallel connection is limited by bandwidth of the number of I/Os, proposed system has no restriction. We evaluate by using three VTR benchmark circuits. As a result, our proposed system can execute 21.2MHz when implementing the circuit which we cannot treat for parallel connected FPGA because of restriction of the number of I/Os. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | / / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 417, RECONF2016-56, pp. 31-36, Jan. 2017. | |
| Paper # | RECONF2016-56 | |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-75 CPSY2016-111 RECONF2016-56 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2017-01-23 - 2017-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2017-01-CPSY-RECONF-VLD-SLDM-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection |
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| 1st Author's Name | Futoshi Murase |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 2nd Author's Name | Daichi Takagi |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 5th Author's Name | Masahiro Iida |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
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| Speaker | Author-1 |
| Date Time | 2017-01-23 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2016-75, CPSY2016-111, RECONF2016-56 |
| Volume (vol) | vol.116 |
| Number (no) | no.415(VLD), no.416(CPSY), no.417(RECONF) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
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