Paper Abstract and Keywords |
Presentation |
2016-11-30 09:50
On SAT based test pattern generation for transition faults considering signal activities Yusuke Matsunaga (Kyushu Univ.) VLD2016-63 DC2016-57 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a test pattern generation method with considering
signal transition activities using a SAT solver.
A simple SAT based test pattern generation method can only find
a single pattern per a fault, which does not consider the signal
transition activities.
The proposed method employs a modified SAT based test pattern
generation algorithm which generates a sum of products form
representing a set of test patterns.
Test patterns are generated using random sampling from the sum product
form, and the best one is selected with respect to the signal
transition activities. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
test pattern generation / signal transition activity / SAT / random sampling / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 330, VLD2016-63, pp. 111-115, Nov. 2016. |
Paper # |
VLD2016-63 |
Date of Issue |
2016-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-63 DC2016-57 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE |
Conference Date |
2016-11-28 - 2016-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2016 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
On SAT based test pattern generation for transition faults considering signal activities |
Sub Title (in English) |
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test pattern generation |
Keyword(2) |
signal transition activity |
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SAT |
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random sampling |
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1st Author's Name |
Yusuke Matsunaga |
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Kyushu University (Kyushu Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-11-30 09:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-63, DC2016-57 |
Volume (vol) |
vol.116 |
Number (no) |
no.330(VLD), no.331(DC) |
Page |
pp.111-115 |
#Pages |
5 |
Date of Issue |
2016-11-21 (VLD, DC) |
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