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Paper Abstract and Keywords
Presentation 2016-11-30 13:20
Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller -- High-Speed Low-Power Reference-Less SAR-ADC --
Tamakoshi Akira, Masanori Natsui, Takahiro Hanyu (Touhoku Univ.) CPM2016-86 ICD2016-47 IE2016-81 Link to ES Tech. Rep. Archives: CPM2016-86 ICD2016-47
Abstract (in Japanese) (See Japanese page) 
(in English) A high-speed low-power successive-approximation-type analog-to-digital converter (SAR ADC) is proposed for a key module of an ultra-low-power nonvolatile micro-controller LSI. First, we suppose that a standard isolation process technology, allowed deep-well structure, can be used in designing the proposed ADC, which enables to set reference voltages for AD conversion as an arbitrary level. In general, it is necessary to set up three kinds of reference voltage in ADC. In the proposed ADC, two of them are set to the same low reference voltage, and the rest is set to a high reference voltage. By using the above formation, by setting a bulk potential at a specific minus voltage, the effect of the variation of the reference voltages can be suppressed and the proposed ADC achieves high-speed and low-power operation.Through a performance evaluation, it is demonstrated that the proposed ADC reduces the power dissipation to 26% of a conventional ADC while maintaining the same degree of operating frequency.
Keyword (in Japanese) (See Japanese page) 
(in English) micorprocessor / SAR ADC / reference voltage / deep well / multilevel supply voltage / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 334, ICD2016-47, pp. 51-56, Nov. 2016.
Paper # ICD2016-47 
Date of Issue 2016-11-22 (CPM, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF CPM2016-86 ICD2016-47 IE2016-81 Link to ES Tech. Rep. Archives: CPM2016-86 ICD2016-47

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE  
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller 
Sub Title (in English) High-Speed Low-Power Reference-Less SAR-ADC 
Keyword(1) micorprocessor  
Keyword(2) SAR ADC  
Keyword(3) reference voltage  
Keyword(4) deep well  
Keyword(5) multilevel supply voltage  
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1st Author's Name Tamakoshi Akira  
1st Author's Affiliation Touhoku University (Touhoku Univ.)
2nd Author's Name Masanori Natsui  
2nd Author's Affiliation Touhoku University (Touhoku Univ.)
3rd Author's Name Takahiro Hanyu  
3rd Author's Affiliation Touhoku University (Touhoku Univ.)
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Date Time 2016-11-30 13:20:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2016-86, ICD2016-47, IE2016-81 
Volume (vol) vol.116 
Number (no) no.333(CPM), no.334(ICD), no.335(IE) 
Page pp.51-56 
#Pages
Date of Issue 2016-11-22 (CPM, ICD, IE) 


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