Paper Abstract and Keywords |
Presentation |
2016-11-30 09:25
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures.
Small delay faults may cause circuit malfunction due to aging deterioration.
Therefore, test method for small delay faults is required.
We have proposed small delay measurement circuit using TDC(Time-to-Digital Converter) to detect small delay faults on circuit paths.
In this paper, we propose new scan FF design that can from a TDC with less area overhead and evaluate its feasibility to detect small delay faults by circuit simulation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
small delay faults / TDC(Time-to-Digital Converter) / design for testability / scan design / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 331, DC2016-56, pp. 105-110, Nov. 2016. |
Paper # |
DC2016-56 |
Date of Issue |
2016-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-62 DC2016-56 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE |
Conference Date |
2016-11-28 - 2016-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2016 -New Field of VLSI Design- |
Paper Information |
Registration To |
DC |
Conference Code |
2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults |
Sub Title (in English) |
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Keyword(1) |
small delay faults |
Keyword(2) |
TDC(Time-to-Digital Converter) |
Keyword(3) |
design for testability |
Keyword(4) |
scan design |
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1st Author's Name |
Shingo Kawatsuka |
1st Author's Affiliation |
Tokushima University (Tokushima Univ.) |
2nd Author's Name |
Hiroyuki Yotsuyanagi |
2nd Author's Affiliation |
Tokushima University (Tokushima Univ.) |
3rd Author's Name |
Masaki Hashizume |
3rd Author's Affiliation |
Tokushima University (Tokushima Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-11-30 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
VLD2016-62, DC2016-56 |
Volume (vol) |
vol.116 |
Number (no) |
no.330(VLD), no.331(DC) |
Page |
pp.105-110 |
#Pages |
6 |
Date of Issue |
2016-11-21 (VLD, DC) |
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