Paper Abstract and Keywords |
Presentation |
2016-11-29 09:25
Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB).
It's a chip for mounting in wearable devices and IoT which has been developed recently.
This time, we report on implementation and evaluation of CMA-Cube-SOTB 2 (CC-SOTB2) which is a new version of CMA developed for 3D stacked chip.
CMA architecture consists of a large scale processing element (PE) array, a microcontroller for managing data transfer, and a data memory.
In CC-SOTB2, power consumption was reduced by optimizing the direct link connecting each PE.
We also implemented a variable pipeline in the PE array.
This realized performance optimization and reduction of extra power consumption by glitch propagation.
As a result, the power efficiency improved by 18% compared with the previous version CC-SOTB. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
reconfigurable / accelerator / CGRA / low power / SOTB / body bias control / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 330, VLD2016-54, pp. 61-66, Nov. 2016. |
Paper # |
VLD2016-54 |
Date of Issue |
2016-11-21 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-54 DC2016-48 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE |
Conference Date |
2016-11-28 - 2016-11-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2016 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Ultra Low Power Reconfigurable Accelerator CC-SOTB2 |
Sub Title (in English) |
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Keyword(1) |
reconfigurable |
Keyword(2) |
accelerator |
Keyword(3) |
CGRA |
Keyword(4) |
low power |
Keyword(5) |
SOTB |
Keyword(6) |
body bias control |
Keyword(7) |
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1st Author's Name |
Koichiro Masuyama |
1st Author's Affiliation |
Keio University (Keio Univ.) |
2nd Author's Name |
Naoki Ando |
2nd Author's Affiliation |
Keio University (Keio Univ.) |
3rd Author's Name |
Yusuke Matsushita |
3rd Author's Affiliation |
Keio University (Keio Univ.) |
4th Author's Name |
Hayate Okuhara |
4th Author's Affiliation |
Keio University (Keio Univ.) |
5th Author's Name |
Hideharu Amano |
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Keio University (Keio Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-11-29 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-54, DC2016-48 |
Volume (vol) |
vol.116 |
Number (no) |
no.330(VLD), no.331(DC) |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2016-11-21 (VLD, DC) |
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