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Paper Abstract and Keywords
Presentation 2016-11-28 13:10
Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)
Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech) VLD2016-47 DC2016-41
Abstract (in Japanese) (See Japanese page) 
(in English) Level shifter is a circuit that changes the voltage amplitude of the signal. It is essential to exchange signals with different power supply voltage area. Level-shifter has the overhead, such as increase in the number of input signals and the circuit area. If the signal connection is possible between the different power supply voltage without inserting a level-shifter, it is possible to eliminate the overhead. In this paper, we propose a method which does not use level-shifters (level-shifter-less method) by applying body bias and Silicon-on-Thin-BOX. Feasibility studies and evaluation for level-shifter-less design is demonstrated by simulation and real chip.
Keyword (in Japanese) (See Japanese page) 
(in English) Level-shifter-less / Body Bias / Silicon-on-Thin-Box(SOTB) / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 330, VLD2016-47, pp. 19-24, Nov. 2016.
Paper # VLD2016-47 
Date of Issue 2016-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-47 DC2016-41

Conference Information
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB) 
Sub Title (in English)  
Keyword(1) Level-shifter-less  
Keyword(2) Body Bias  
Keyword(3) Silicon-on-Thin-Box(SOTB)  
1st Author's Name Shunsuke Kogure  
1st Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (Shibaura Institute of Tech)
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Date Time 2016-11-28 13:10:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2016-47,IEICE-DC2016-41 
Volume (vol) IEICE-116 
Number (no) no.330(VLD), no.331(DC) 
Page pp.19-24 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2016-11-21,IEICE-DC-2016-11-21 

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