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Paper Abstract and Keywords
Presentation 2016-10-26 15:30
[Invited Talk] Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation
Hideki Makiyama, Yoshiki Yamamoto, Takumi Hasegawa, Shinobu Okanishi, Keiichi Maekawa, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi (Renesas Electronics Corp.), Nobuyuki Sugii (Hitach), Koichiro Ishibashi (The Univ. of Electro-Communications), Tomoko Mizutani, Toshiro Hiramoto (The Univ. of Tokyo) SDM2016-71 Link to ES Tech. Rep. Archives: SDM2016-71
Abstract (in Japanese) (See Japanese page) 
(in English) Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.
Keyword (in Japanese) (See Japanese page) 
(in English) SOTB / SOI / back bias / ring oscillator / Tpd / variability / ultra-low voltage /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 270, SDM2016-71, pp. 15-20, Oct. 2016.
Paper # SDM2016-71 
Date of Issue 2016-10-19 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF SDM2016-71 Link to ES Tech. Rep. Archives: SDM2016-71

Conference Information
Committee SDM  
Conference Date 2016-10-26 - 2016-10-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Niche, Tohoku Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process Science and New Process Technology 
Paper Information
Registration To SDM 
Conference Code 2016-10-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Back-Bias Control Technique for Suppression of Die-to-Die Delay Variability of SOTB CMOS Circuits at Ultralow-Voltage (0.4 V) Operation 
Sub Title (in English)  
Keyword(1) SOTB  
Keyword(2) SOI  
Keyword(3) back bias  
Keyword(4) ring oscillator  
Keyword(5) Tpd  
Keyword(6) variability  
Keyword(7) ultra-low voltage  
Keyword(8)  
1st Author's Name Hideki Makiyama  
1st Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
2nd Author's Name Yoshiki Yamamoto  
2nd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
3rd Author's Name Takumi Hasegawa  
3rd Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
4th Author's Name Shinobu Okanishi  
4th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
5th Author's Name Keiichi Maekawa  
5th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
6th Author's Name Hiroki Shinkawata  
6th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
7th Author's Name Shiro Kamohara  
7th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
8th Author's Name Yasuo Yamaguchi  
8th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics Corp.)
9th Author's Name Nobuyuki Sugii  
9th Author's Affiliation Hitachi Ltd (Hitach)
10th Author's Name Koichiro Ishibashi  
10th Author's Affiliation The University of Electro-Communications (The Univ. of Electro-Communications)
11th Author's Name Tomoko Mizutani  
11th Author's Affiliation The Universty of Tokyo (The Univ. of Tokyo)
12th Author's Name Toshiro Hiramoto  
12th Author's Affiliation The Universty of Tokyo (The Univ. of Tokyo)
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Speaker
Date Time 2016-10-26 15:30:00 
Presentation Time 40 
Registration for SDM 
Paper # IEICE-SDM2016-71 
Volume (vol) IEICE-116 
Number (no) no.270 
Page pp.15-20 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2016-10-19 


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