Paper Abstract and Keywords |
Presentation |
2016-10-20 13:50
Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT) NS2016-90 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to improve forwarding performance. In this paper, we propose distributed architecture utilizing hardware accelerators with high-level synthesis technology for virtualized service edge functions to satisfy migration constraints and to improve forwarding throughput. Furthermore, we evaluate improvement of forwarding performance in proposed method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Virtualized Service Edge Router / Hardware Accelerator / High-Level Synthesis / Network Function Virtualization / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 256, NS2016-90, pp. 13-18, Oct. 2016. |
Paper # |
NS2016-90 |
Date of Issue |
2016-10-13 (NS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NS2016-90 |
Conference Information |
Committee |
NS |
Conference Date |
2016-10-20 - 2016-10-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Himeji Nishi-Harima Area Jibasan Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
NS |
Conference Code |
2016-10-NS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router |
Sub Title (in English) |
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Keyword(1) |
Virtualized Service Edge Router |
Keyword(2) |
Hardware Accelerator |
Keyword(3) |
High-Level Synthesis |
Keyword(4) |
Network Function Virtualization |
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1st Author's Name |
Satoshi Nishiyama |
1st Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
2nd Author's Name |
Hitoshi Kaneko |
2nd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
3rd Author's Name |
Ichiro Kudo |
3rd Author's Affiliation |
Nippon Telegraph and Telephone Corporation (NTT) |
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Speaker |
Author-1 |
Date Time |
2016-10-20 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
NS |
Paper # |
NS2016-90 |
Volume (vol) |
vol.116 |
Number (no) |
no.256 |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2016-10-13 (NS) |