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Paper Abstract and Keywords
Presentation 2016-09-06 09:10
[Invited Talk] Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)
Abstract (in Japanese) (See Japanese page) 
(in English) CPU-FPGA tightly coupled architecture is an emerging architecture where FPGA is tightly coupled with CPU. We introduce an acceleration method that exploits the CPU-FPGA tightly coupled architecture. The advantages of such CPU-FPGA tightly coupled architecture include a broadband interconnect for the main memory space shared by CPU and FPGA. However, it requires careful design of both hardware and software to fully exploit the potential communication performance of the architecture. We developed a data packing technique to improve the efficiency of communication, and communication scheme that utilizes ring queues. We applied the developed techniques to an IoT application that performs the high-accuracy analysis of real world and confirmed that they are effective for accelerating the kernel function of the application.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / CPU-FPGA tightly coupled architecture / IoT / Ring-queue / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 210, RECONF2016-32, pp. 37-37, Sept. 2016.
Paper # RECONF2016-32 
Date of Issue 2016-08-29 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.

Conference Information
Committee RECONF  
Conference Date 2016-09-05 - 2016-09-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Univ. of Toyama 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2016-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) CPU-FPGA tightly coupled architecture  
Keyword(3) IoT  
Keyword(4) Ring-queue  
1st Author's Name Yuki Kobayashi  
1st Author's Affiliation NEC Corporation (NEC)
2nd Author's Name Yoshikazu Watanabe  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Seiya Shibata  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Takashi Takenaka  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Takeo Hosomi  
5th Author's Affiliation NEC Corporation (NEC)
6th Author's Name Yuichi Nakamura  
6th Author's Affiliation NEC Corporation (NEC)
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Date Time 2016-09-06 09:10:00 
Presentation Time 50 
Registration for RECONF 
Paper # IEICE-RECONF2016-32 
Volume (vol) IEICE-116 
Number (no) no.210 
Page p.37 
#Pages IEICE-1 
Date of Issue IEICE-RECONF-2016-08-29 

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