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Paper Abstract and Keywords
Presentation 2016-07-21 13:45
On Efficient FPGA Implementation of PAPR Reduction Based on Trellis Shaping for OFDM Systems
Jiajia Song, Hideki Ochiai (YNU)
Abstract (in Japanese) (See Japanese page) 
(in English) Given the fact that the implementation of trellis shaping (TS) requires a large number of multipliers, its practical application to PAPR reduction of OFDM signal is considered to be challenging. In view of this, we present an FPGA implementation of TS for PAPR reduction of OFDM signals. We focus on its hardware resource consumption and develop a cost-effective approach that leads to efficient implementation of its functionality. The experimental results show that TS can be realized with a reasonable size of hardware resources based on the proposed approach on a Virtex-7 FPGA. Moreover, a trellis window truncation method of TS that allows us to significantly reduce its computational complexity is also implemented, which enables an efficient
PAPR reduction of 256-subcarrier OFDM signals with limited hardware resources.
Keyword (in Japanese) (See Japanese page) 
(in English) Trellis Shaping / FPGA Implementation / PAPR Reduction / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 147, RCS2016-120, pp. 133-138, July 2016.
Paper # RCS2016-120 
Date of Issue 2016-07-13 (RCS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee RCS RCC ASN NS SR  
Conference Date 2016-07-20 - 2016-07-22 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Wireless Distributed Network, M2M: Machine-to-Machine, D2D (Device-to-Device),etc. 
Paper Information
Registration To RCS 
Conference Code 2016-07-RCS-RCC-ASN-NS-SR 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On Efficient FPGA Implementation of PAPR Reduction Based on Trellis Shaping for OFDM Systems 
Sub Title (in English)  
Keyword(1) Trellis Shaping  
Keyword(2) FPGA Implementation  
Keyword(3) PAPR Reduction  
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1st Author's Name Jiajia Song  
1st Author's Affiliation Yokohama National Univiersity (YNU)
2nd Author's Name Hideki Ochiai  
2nd Author's Affiliation Yokohama National Univiersity (YNU)
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Speaker
Date Time 2016-07-21 13:45:00 
Presentation Time 25 
Registration for RCS 
Paper # IEICE-RCS2016-120 
Volume (vol) IEICE-116 
Number (no) no.147 
Page pp.133-138 
#Pages IEICE-6 
Date of Issue IEICE-RCS-2016-07-13 


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