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Paper Abstract and Keywords
Presentation 2016-06-29 10:40
[Invited Lecture] Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators
Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-34 Link to ES Tech. Rep. Archives: SDM2016-34
Abstract (in Japanese) (See Japanese page) 
(in English) This paper discusses a design of fully depleted silicon-on-insulator field-effect transistors with ferroelectric gate insulators to attain a steep subthreshold swing (SS) by exploiting the negative capacitance. Our technology computer aided design simulation reveals that not only appropriate thickness of SOI and the ferroelectric layer but also an ulthathin buried oxide which enables to make voltage drop in the ferroelectric gate layer effectively is crucial to attain less than 60 mV/decade in a wide range of the gate voltage under the threshold voltage.
Keyword (in Japanese) (See Japanese page) 
(in English) negative capacitance / ferroelectric / steep subthreshold swing / silicon-on-insulator / ow voltage operation / MOSFET / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 118, SDM2016-34, pp. 9-13, June 2016.
Paper # SDM2016-34 
Date of Issue 2016-06-22 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2016-34 Link to ES Tech. Rep. Archives: SDM2016-34

Conference Information
Committee SDM  
Conference Date 2016-06-29 - 2016-06-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Campus Innovation Center Tokyo 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Material Science and Process Technology for MOS Devices and Memories 
Paper Information
Registration To SDM 
Conference Code 2016-06-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators 
Sub Title (in English)  
Keyword(1) negative capacitance  
Keyword(2) ferroelectric  
Keyword(3) steep subthreshold swing  
Keyword(4) silicon-on-insulator  
Keyword(5) ow voltage operation  
Keyword(6) MOSFET  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroyuki Ota  
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Shinji Migita  
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
3rd Author's Name Junichi Hattori  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
4th Author's Name Koichi Fukuda  
4th Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
5th Author's Name Akira Toriumi  
5th Author's Affiliation The Univsityer of Tokyo (The Univ. of Tokyo)
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Speaker Author-1 
Date Time 2016-06-29 10:40:00 
Presentation Time 20 minutes 
Registration for SDM 
Paper # SDM2016-34 
Volume (vol) vol.116 
Number (no) no.118 
Page pp.9-13 
#Pages
Date of Issue 2016-06-22 (SDM) 


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