Paper Abstract and Keywords |
Presentation |
2016-06-29 10:40
[Invited Lecture]
Design of SOI-FETs for Steep Slope Switching using Negative Capacitance in Ferroelectric Gate Insulators Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2016-34 Link to ES Tech. Rep. Archives: SDM2016-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper discusses a design of fully depleted silicon-on-insulator field-effect transistors with ferroelectric gate insulators to attain a steep subthreshold swing (SS) by exploiting the negative capacitance. Our technology computer aided design simulation reveals that not only appropriate thickness of SOI and the ferroelectric layer but also an ulthathin buried oxide which enables to make voltage drop in the ferroelectric gate layer effectively is crucial to attain less than 60 mV/decade in a wide range of the gate voltage under the threshold voltage. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
negative capacitance / ferroelectric / steep subthreshold swing / silicon-on-insulator / ow voltage operation / MOSFET / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 118, SDM2016-34, pp. 9-13, June 2016. |
Paper # |
SDM2016-34 |
Date of Issue |
2016-06-22 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2016-34 Link to ES Tech. Rep. Archives: SDM2016-34 |