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Paper Abstract and Keywords
Presentation 2016-06-20 14:15
Relationship between the Number of Fan-Outs and Its Wire-length for a logic gate
Taiki Kobayashi, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DC2016-12
Abstract (in Japanese) (See Japanese page) 
(in English) Many analysis and algorithms have been proposed to reduce wire-lengths based on Steiner trees for VLSI layout designs. As a number of fan-outs for a gate increases, the wire-length for the gate gets longer. There is very few work to practically investigate the relationship between the number of fan-outs and the wire-length. In order to figure the relation layouts are designed for twenty six ISCAS benchmark circuits. Then, the number of fan-outs and wire-lengths are examined. Among twenty six designs ten layouts have a gate gates that have more than or equal to thirty fan-outs. For these ten circuits power-law approximation provides nearly equal or more preferable values than those obtained by linear approximation for estimating wire-length as a function of fan-outs.
Keyword (in Japanese) (See Japanese page) 
(in English) VLSI Layout / Steiner Tree / Wire-Length / Number of Fan-Outs / Coefficient of Determianation / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 108, DC2016-12, pp. 13-18, June 2016.
Paper # DC2016-12 
Date of Issue 2016-06-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2016-06-20 - 2016-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification, etc. 
Paper Information
Registration To DC 
Conference Code 2016-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Relationship between the Number of Fan-Outs and Its Wire-length for a logic gate 
Sub Title (in English)  
Keyword(1) VLSI Layout  
Keyword(2) Steiner Tree  
Keyword(3) Wire-Length  
Keyword(4) Number of Fan-Outs  
Keyword(5) Coefficient of Determianation  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Taiki Kobayashi  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Kazuhiko Iwasaki  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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Speaker Author-1 
Date Time 2016-06-20 14:15:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2016-12 
Volume (vol) vol.116 
Number (no) no.108 
Page pp.13-18 
#Pages
Date of Issue 2016-06-13 (DC) 


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