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| Presentation | 2016-05-20 11:55 Interface control for III-V/Si hetero-epitaxy Keisuke Yamane, Hiroto Sekiguchi (Toyohashi Tech.), Hiroshi Okada (EIIRIS), Akihiro Wakahara (Toyohashi Tech.)  ED2016-26 CPM2016-14 SDM2016-31 Link to ES Tech. Rep. Archives: ED2016-26 CPM2016-14 SDM2016-31 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper focuses a formation process of the first atomic layer on Si substrates for GaP/Si heteroepitaxy. It is clarified that surface states of vicinal Si substrates strongly affects a generation of anti-phase domains (APDs) in GaP layers. When P2-molecular-beam was irradiated on vicinal Si substrates at higher temperature (over 640°C), step-bunching with multi-atomic steps occurred, resulting in a formation of wide terraces on the substrate. In the GaP layers grown on a step-bunched Si surfece, relatively large APDs were generated. The terrace-width of the step-bunched Si surface was close to the mean width of the APD-base. Therefore, it is of particular importance that the growth starts at the temperature range that single atomic layer is kept during the P2-molecular-beam irradiation before the growth. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Si / GaP / Anti-phase domain / step-bunching / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 48, ED2016-26, pp. 61-65, May 2016. | |
| Paper # | ED2016-26 | |
| Date of Issue | 2016-05-12 (ED, CPM, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ED2016-26 CPM2016-14 SDM2016-31 Link to ES Tech. Rep. Archives: ED2016-26 CPM2016-14 SDM2016-31 |
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| Conference Information | |
| Committee | CPM ED SDM |
| Conference Date | 2016-05-19 - 2016-05-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shizuoka University, Hamamatsu campus (Joint Research Lab.) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | crystal growth、devices characterization , etc. |
| Paper Information | |
| Registration To | ED |
| Conference Code | 2016-05-CPM-ED-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Interface control for III-V/Si hetero-epitaxy |
| Sub Title (in English) | |
| Keyword(1) | Si |
| Keyword(2) | GaP |
| Keyword(3) | Anti-phase domain |
| Keyword(4) | step-bunching |
| Keyword(5) | |
| Keyword(6) | |
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| 1st Author's Name | Keisuke Yamane |
| 1st Author's Affiliation | Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology (Toyohashi Tech.) |
| 2nd Author's Name | Hiroto Sekiguchi |
| 2nd Author's Affiliation | Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology (Toyohashi Tech.) |
| 3rd Author's Name | Hiroshi Okada |
| 3rd Author's Affiliation | Electronics-Inspired Interdisciplinary Research Institute, Toyohashi University of Technology (EIIRIS) |
| 4th Author's Name | Akihiro Wakahara |
| 4th Author's Affiliation | Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology (Toyohashi Tech.) |
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| Speaker | Author-1 |
| Date Time | 2016-05-20 11:55:00 |
| Presentation Time | 25 minutes |
| Registration for | ED |
| Paper # | ED2016-26, CPM2016-14, SDM2016-31 |
| Volume (vol) | vol.116 |
| Number (no) | no.48(ED), no.49(CPM), no.50(SDM) |
| Page | pp.61-65 |
| #Pages | 5 |
| Date of Issue | 2016-05-12 (ED, CPM, SDM) |
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