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| Presentation | 2016-04-14 10:10 [Invited Lecture] A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics)  ICD2016-1 Link to ES Tech. Rep. Archives: ICD2016-1 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micro controller units (MCUs). The probing test step at low-temperature (LT) of -40°C is eliminated by imitating pseudo LT conditions in the final test step where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out with consideration of global and local Vt variations as well as contact soft open failure (high resistance), confirming good Vmin correlation between LT and pseudo LT conditions. Test chips with a 4-Mbit SRAM macro are designed and fabricated using 40-nm low-power CMOS technology. Measurement results show that the proposed test method can reproduce LT conditions and screen out low temperature failures with less overkill. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SRAM / MCU / 40nm / screening / 40℃ / testability / test cost / Vmin | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 3, ICD2016-1, pp. 1-6, April 2016. | |
| Paper # | ICD2016-1 | |
| Date of Issue | 2016-04-07 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2016-1 Link to ES Tech. Rep. Archives: ICD2016-1 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2016-04-14 - 2016-04-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2016-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | MCU |
| Keyword(3) | 40nm |
| Keyword(4) | screening |
| Keyword(5) | 40℃ |
| Keyword(6) | testability |
| Keyword(7) | test cost |
| Keyword(8) | Vmin |
| 1st Author's Name | Yuta Yoshida |
| 1st Author's Affiliation | Renesas System Design (RSD) |
| 2nd Author's Name | Yoshisato Yokoyama |
| 2nd Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 3rd Author's Name | Yuichiro Ishii |
| 3rd Author's Affiliation | Renesas Electronics (Renesas Electronics) |
| 4th Author's Name | Toshihiro Inada |
| 4th Author's Affiliation | Renesas System Design (RSD) |
| 5th Author's Name | Koji Tanaka |
| 5th Author's Affiliation | Renesas System Design (RSD) |
| 6th Author's Name | Miki Tanaka |
| 6th Author's Affiliation | Renesas System Design (RSD) |
| 7th Author's Name | Yoshiki Tsujihashi |
| 7th Author's Affiliation | Renesas System Design (RSD) |
| 8th Author's Name | Koji Nii |
| 8th Author's Affiliation | Renesas Electronics (Renesas Electronics) |
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| Speaker | Author-1 |
| Date Time | 2016-04-14 10:10:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2016-1 |
| Volume (vol) | vol.116 |
| Number (no) | no.3 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2016-04-07 (ICD) |
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