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| Presentation | 2016-03-25 14:30 Design Evaluation of Low-Latency Handshake Join on FPGA Masato Yoshimi, Yasin Oge, Celimuge Wu, Tsutomu Yoshinaga (UEC)  CPSY2015-155 DC2015-109 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency (e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / query processing / data stream / sliding-window join / low-latency handshake join / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 518, CPSY2015-155, pp. 253-258, March 2016. | |
| Paper # | CPSY2015-155 | |
| Date of Issue | 2016-03-17 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | CPSY2015-155 DC2015-109 |
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| Conference Information | |
| Committee | CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC |
| Conference Date | 2016-03-24 - 2016-03-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Fukue Bunka Hall/Rodou Fukushi Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2016 |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2016-03-CPSY-DC-SLDM-EMB-ARC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Evaluation of Low-Latency Handshake Join on FPGA |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | query processing |
| Keyword(3) | data stream |
| Keyword(4) | sliding-window join |
| Keyword(5) | low-latency handshake join |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masato Yoshimi |
| 1st Author's Affiliation | University of Electro-Communications (UEC) |
| 2nd Author's Name | Yasin Oge |
| 2nd Author's Affiliation | University of Electro-Communications (UEC) |
| 3rd Author's Name | Celimuge Wu |
| 3rd Author's Affiliation | University of Electro-Communications (UEC) |
| 4th Author's Name | Tsutomu Yoshinaga |
| 4th Author's Affiliation | University of Electro-Communications (UEC) |
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| Speaker | Author-1 |
| Date Time | 2016-03-25 14:30:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2015-155, DC2015-109 |
| Volume (vol) | vol.115 |
| Number (no) | no.518(CPSY), no.519(DC) |
| Page | pp.253-258 |
| #Pages | 6 |
| Date of Issue | 2016-03-17 (CPSY, DC) |
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