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| Presentation | 2016-03-01 10:55 Power Analysis Attack for Countermeasure with Check Circuit Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ.)  VLD2015-122 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The thread of side-channel attack against cryptgraphic circuit is pointed out. Side-channel attack is classified into two attack methods; fault analysis attack and power analysis attack. A fault analysis attack intentionally generates operation errors during the encryption processing, and obtains confidential information using pairs of an incorrect cryptogram and a correct one. A method using a check circuit was reported as a typical measure against a fault analysis attack. A power analysis attack uses the correlation between encryption processing and power consumption. However, there is no report of which a power analysis attack is applied to check circuit. Therefore, this study proposes a new power analysis method for AES with check circuit. Experiments using an actual device prove the validity of the proposed method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | AES / Power Analysis Attack / Check Circuit / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 465, VLD2015-122, pp. 67-72, Feb. 2016. | |
| Paper # | VLD2015-122 | |
| Date of Issue | 2016-02-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-122 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2016-02-29 - 2016-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2016-02-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis Attack for Countermeasure with Check Circuit |
| Sub Title (in English) | |
| Keyword(1) | AES |
| Keyword(2) | Power Analysis Attack |
| Keyword(3) | Check Circuit |
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| 1st Author's Name | Yoshiya Ikezaki |
| 1st Author's Affiliation | Meijo University (Meijo Univ.) |
| 2nd Author's Name | Masaya Yoshikawa |
| 2nd Author's Affiliation | Meijo University (Meijo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2016-03-01 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-122 |
| Volume (vol) | vol.115 |
| Number (no) | no.465 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2016-02-22 (VLD) |
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