Paper Abstract and Keywords |
Presentation |
2016-03-01 15:10
FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing and computerized stock trading.
With recent process scaling in FPGAs, the impact of wire delays becomes bottle neck and there are two effective techniques for solving this problem, ``floorplan-aware FPGA-HLS" which enables us to estimate the impact of wire delays in HLS stage and ``distributed-register architecture" which can reduce wire delays between functional units and registers.
In this paper, we implement a distributed-register circuit of DCT application by applying the floorplan-aware FPGA-HLS for HDR architecture.
We verify the operation of the circuit on an FPGA chip and evaluate its performance.
Our implemented circuit can reduce the latency by 22% compared with the traditional shared-register circuit. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
high-level synthesis (HLS) / FPGA / distributed-register architecture / floorplan / interconnection delay / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 465, VLD2015-127, pp. 93-98, Feb. 2016. |
Paper # |
VLD2015-127 |
Date of Issue |
2016-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2015-127 |
Conference Information |
Committee |
VLD |
Conference Date |
2016-02-29 - 2016-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
|
Paper Information |
Registration To |
VLD |
Conference Code |
2016-02-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis |
Sub Title (in English) |
|
Keyword(1) |
high-level synthesis (HLS) |
Keyword(2) |
FPGA |
Keyword(3) |
distributed-register architecture |
Keyword(4) |
floorplan |
Keyword(5) |
interconnection delay |
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Koichi Fujiwara |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Kawamura Kazushi |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Keita Igarashi |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Masao Yanagisawa |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Nozomu Togawa |
5th Author's Affiliation |
Waseda University (Waseda Univ.) |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2016-03-01 15:10:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-127 |
Volume (vol) |
vol.115 |
Number (no) |
no.465 |
Page |
pp.93-98 |
#Pages |
6 |
Date of Issue |
2016-02-22 (VLD) |
|