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| Presentation | 2016-02-29 16:15 A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis Keisuke Inoue (KTC), Mineo Kaneko (JAIST)  VLD2015-117 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls. The disadvantage of the conventional latch-based architecture is the area overhead due to the increase of resources (functional units and registers). Its impact becomes relatively larger and larger in deep sub-micron technology era. Our main idea is to insert and control a circuit element namely gating element (GE) into the datapath. GE supports the correct data propagation, and mitigates the conventional resource sharing conditions, thereby helps reducing the area cost. We point out that in the proposed design, different resource bindings (functional unit binding and register binding) require the different number of GEs. We initially discuss the problem of resource binding to minimize the number of GEs for datapath cost reduction. To solve this problem, we propose a path-based heuristic algorithm to obtain near optimal solutions, and an ILP-based algorithm to obtain exact solutions. The experiments using benchmarks confirm the effectiveness of our approaches. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | latch / HLS / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 465, VLD2015-117, pp. 37-42, Feb. 2016. | |
| Paper # | VLD2015-117 | |
| Date of Issue | 2016-02-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-117 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2016-02-29 - 2016-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2016-02-VLD |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | latch |
| Keyword(2) | HLS |
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| 1st Author's Name | Keisuke Inoue |
| 1st Author's Affiliation | Kanazawa Technical College (KTC) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
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| Speaker | Author-1 |
| Date Time | 2016-02-29 16:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-117 |
| Volume (vol) | vol.115 |
| Number (no) | no.465 |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2016-02-22 (VLD) |
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