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Paper Abstract and Keywords
Presentation 2016-02-29 16:15
A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis
Keisuke Inoue (KTC), Mineo Kaneko (JAIST)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls.
The disadvantage of the conventional latch-based architecture is the area overhead
due to the increase of resources (functional units and registers).
Its impact becomes relatively larger and larger in deep sub-micron technology era.
Our main idea is to insert and control a circuit element namely gating element (GE) into the datapath.
GE supports the correct data propagation, and
mitigates the conventional resource sharing conditions, thereby helps reducing the area cost.
We point out that in the proposed design,
different resource bindings (functional unit binding and register binding)
require the different number of GEs.
We initially discuss the problem of resource binding
to minimize the number of GEs for datapath cost reduction.
To solve this problem, we propose a path-based heuristic algorithm
to obtain near optimal solutions, and an ILP-based algorithm
to obtain exact solutions.
The experiments using benchmarks confirm the effectiveness of
our approaches.
Keyword (in Japanese) (See Japanese page) 
(in English) latch / HLS / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 465, VLD2015-117, pp. 37-42, Feb. 2016.
Paper # VLD2015-117 
Date of Issue 2016-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee VLD  
Conference Date 2016-02-29 - 2016-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2016-02-VLD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis 
Sub Title (in English)  
Keyword(1) latch  
Keyword(2) HLS  
1st Author's Name Keisuke Inoue  
1st Author's Affiliation Kanazawa Technical College (KTC)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Date Time 2016-02-29 16:15:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-117 
Volume (vol) IEICE-115 
Number (no) no.465 
Page pp.37-42 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2016-02-22 

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