Paper Abstract and Keywords |
Presentation |
2016-02-17 11:30
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2015-89 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Stochastic computing, which is a computational scheme with probabilities, is notable for its applicability to error tolerant applications. In this study, we discuss a dynamic share of consecutive bit sequences, which are called stochastic numbers, in order to accelerate stochastic computing.
A basic idea of dynamic share of consecutive stochastic numbers has been presented. We consider the feasibility of this dynamic share of stochastic numbers, and then propose a hardware architecture for implementing this dynamic share. Moreover, based on discussion of area efficiency of the hardware, we propose an algorithm, which is called a selection method, to determine the length of bit sharing. Experimental results show that the proposed method can accelerate stochastic computing with small hardware cost. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Error tolerant application / Stochastic number / Transformation error / Correlation-induced error / Bit sharing / Area efficiency / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 449, DC2015-89, pp. 19-24, Feb. 2016. |
Paper # |
DC2015-89 |
Date of Issue |
2016-02-10 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2015-89 |
Conference Information |
Committee |
DC |
Conference Date |
2016-02-17 - 2016-02-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
VLSI Design and Test, etc. |
Paper Information |
Registration To |
DC |
Conference Code |
2016-02-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences |
Sub Title (in English) |
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Keyword(1) |
Error tolerant application |
Keyword(2) |
Stochastic number |
Keyword(3) |
Transformation error |
Keyword(4) |
Correlation-induced error |
Keyword(5) |
Bit sharing |
Keyword(6) |
Area efficiency |
Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Kensuke Takamori |
1st Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
2nd Author's Name |
Hideyuki Ichihara |
2nd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
3rd Author's Name |
Tsuyoshi Iwagaki |
3rd Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
4th Author's Name |
Tomoo Inoue |
4th Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-02-17 11:30:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2015-89 |
Volume (vol) |
vol.115 |
Number (no) |
no.449 |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2016-02-10 (DC) |
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