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| Paper Abstract and Keywords | ||
| Presentation | 2016-02-17 10:25 Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech)  DC2015-87 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Both logic paths and clock paths are subject to the impact of IR-Drop which occurs in capture mode during scan test. This paper describes a new method for generating high-quality capture-power-safe at-speed scan test vectors by adjusting the impact of IR-Drop on both logic and clock paths. Experimental results on large benchmark circuits have shown the effectiveness of the proposed method. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | At-Speed Scan Test / IR-Drop / Clock Stretch / Capture-Power-Safety / Test Quality / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 449, DC2015-87, pp. 7-12, Feb. 2016. | |
| Paper # | DC2015-87 | |
| Date of Issue | 2016-02-10 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2015-87 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2016-02-17 - 2016-02-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2016-02-DC |
| Language | English (Japanese title is available) |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation |
| Sub Title (in English) | |
| Keyword(1) | At-Speed Scan Test |
| Keyword(2) | IR-Drop |
| Keyword(3) | Clock Stretch |
| Keyword(4) | Capture-Power-Safety |
| Keyword(5) | Test Quality |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Fuqiang Li |
| 1st Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 2nd Author's Name | Xiaoqing Wen |
| 2nd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 3rd Author's Name | Stefan Holst |
| 3rd Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 4th Author's Name | Kohei Miyase |
| 4th Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
| 5th Author's Name | Seiji Kajihara |
| 5th Author's Affiliation | Kyushu Institute of Technology (Kyutech) |
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| Speaker | Author-1 |
| Date Time | 2016-02-17 10:25:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2015-87 |
| Volume (vol) | vol.115 |
| Number (no) | no.449 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2016-02-10 (DC) |
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