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| Presentation | 2016-02-17 10:50 Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)  DC2015-88 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic value of an open fault is controlled by the coupling capacitances between the floating line and its adjacent lines, the open fault can be detected as a stack-at fault. A large-scale integrated circuit having many adjacent lines requires much test generation time. In this study, we propose a method for selecting adjacent lines when assigning logic values in test pattern generation for open faults to reduce computational time. We extract adjacent lines from the ISCAS89 benchmark and evaluate the effectiveness of the proposed method by using ATPG and fault simulator for detecting open faults considering the effects of its adjacent lines. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Open fault / Adjacent line / Open fault ATPG / Coupling capacitance / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 449, DC2015-88, pp. 13-18, Feb. 2016. | |
| Paper # | DC2015-88 | |
| Date of Issue | 2016-02-10 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2015-88 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2016-02-17 - 2016-02-17 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2016-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value |
| Sub Title (in English) | |
| Keyword(1) | Open fault |
| Keyword(2) | Adjacent line |
| Keyword(3) | Open fault ATPG |
| Keyword(4) | Coupling capacitance |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazui Fujitnai |
| 1st Author's Affiliation | Tokushima University (Tokushima Univ.) |
| 2nd Author's Name | Hiroyuki Yotsuyanagi |
| 2nd Author's Affiliation | Tokushima University (Tokushima Univ.) |
| 3rd Author's Name | Masaki Hashizume |
| 3rd Author's Affiliation | Tokushima University (Tokushima Univ.) |
| 4th Author's Name | Yoshinobu Higami |
| 4th Author's Affiliation | Ehime University (Ehime Univ.) |
| 5th Author's Name | Hiroshi Takahashi |
| 5th Author's Affiliation | Ehime University (Ehime Univ.) |
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| Speaker | Author-1 |
| Date Time | 2016-02-17 10:50:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2015-88 |
| Volume (vol) | vol.115 |
| Number (no) | no.449 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2016-02-10 (DC) |
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