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Paper Abstract and Keywords
Presentation 2016-02-17 14:50
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU) DC2015-93
Abstract (in Japanese) (See Japanese page) 
(in English) Test point insertion methods to reduce the number of test patterns have been proposed for test cost reduction of VLSIs. Test point insertion methods at gate level requires an enormous amount of time to identify signal lines to insert test points for large circuits. Additional multiplexors make them damage timing optimality by logic synthesis. Thus, test point insertion methods at RTL is required. In this paper, we propose a test register allocation method for concurrent testing of functional units in scan testing using RTL test point insertion. Furthermore, we propose a controller augmentation method for guaranteeing the behavior. Experimental results show that our proposed method which is the combination of the test register allocation method and the controller augmentation method reduced the number of test patterns by 17 % on the average for benchmark circuits of high-level synthesis.
Keyword (in Japanese) (See Japanese page) 
(in English) test registers / parallel testing / conrtoller augmentation / register transfer level / test point insertion / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 449, DC2015-93, pp. 43-48, Feb. 2016.
Paper # DC2015-93 
Date of Issue 2016-02-10 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2016-02-17 - 2016-02-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2016-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An RTL Test Point Insertion Method to Reduce the Number of Test Patterns 
Sub Title (in English)  
Keyword(1) test registers  
Keyword(2) parallel testing  
Keyword(3) conrtoller augmentation  
Keyword(4) register transfer level  
Keyword(5) test point insertion  
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1st Author's Name Naoya Ohsaki  
1st Author's Affiliation Nihon University (NU)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (NU)
3rd Author's Name Hiroshi Yamazaki  
3rd Author's Affiliation Nihon University (NU)
4th Author's Name Masayoshi Yoshimura  
4th Author's Affiliation Kyoto Sangyo University (KSU)
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Speaker
Date Time 2016-02-17 14:50:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2015-93 
Volume (vol) IEICE-115 
Number (no) no.449 
Page pp.43-48 
#Pages IEICE-6 
Date of Issue IEICE-DC-2016-02-10 


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