Paper Abstract and Keywords |
Presentation |
2016-01-22 10:05
[Invited Talk]
Reliability Results of 4 million Micro Bump Interconnections of 3D Stacked 16 M Pixel Image Sensor Yoshiaki Takemoto, Naohiro Takazawa, Mitsuhiro Tsukimura, Haruhisa Saito, Toru Kondo, Hideki Kato, Jun Aoki, Kenji Kobayashi, Shunsuke Suzuki, Yuichi Gomi, Seisuke Matsuda, Yoshitaka Tadaki (Olympus) SDM2015-108 Link to ES Tech. Rep. Archives: SDM2015-108 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We evaluated the reliability of 3D stacked CMOS image sensors (CISs) with 4 million micro bump inter-connections at a 7.6-um pitch bonded with wafer bonding technology. This 3D stacked technology was proved to have no negative effect on CIS characteristics and to provide a high density and narrow pitched in-pixel connection with high reliability, no defects, and no deteriorations over a 1000-cycle heat cycle test and 1000-hour high temperature and high humidity test. This CIS sensor has a set of readout circuits in each substrate, which enable us to detect any connection failure among 4 million micro bumps between substrates individually. These results show that this 3D technology has enough reliability for application to products. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS Image Sensor / 3D Stacked structure / Micro-Bump / Reliability / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 417, SDM2015-108, pp. 1-4, Jan. 2016. |
Paper # |
SDM2015-108 |
Date of Issue |
2016-01-15 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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SDM2015-108 Link to ES Tech. Rep. Archives: SDM2015-108 |
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