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Paper Abstract and Keywords
Presentation 2016-01-21 09:50
FPGA Implementation of a Peak Detection System using AMPD Algorithm
Fumihiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ) VLD2015-100 CPSY2015-132 RECONF2015-82
Abstract (in Japanese) (See Japanese page) 
(in English) Peak detection of time-series data is widely used in various
applications. A demand for implementation of low-latency and
non-storing real-time peak detection has been increasing, reflecting
recent technical trends such as big-data analysis and the Internet of
things (IoT). This paper presents hardware architecture and FPGA
implementation of a real-time and low-latency peak detection mechanism
based on the automatic multi-scale based peak detection (AMPD) method,
which is an algorithms of peak detection with multi-scale windows for
quasi-periodic input signals. Empirical experiments show the algorithm
can be efficiently implemented on a small FPGA with a good detection
accuracy, depending on a relationship between a frequency of the input
signal and a sampling rate. Peak detection of time-series data is widely used in various
applications. A demand for implementation of low-latency and non-storing real-time peak detection has been increasing, reflecting recent technical trends such as big-data analysis and the Internet of things (IoT). This paper presents hardware architecture and FPGA implementation of a real-time and low-latency peak detection mechanism based on the automatic multi-scale based peak detection (AMPD) method,which is an algorithms of peak detection with multi-scale windows for quasi-periodic input signals. Empirical experiments show the algorithm can be efficiently implemented on a small FPGA with a good detection accuracy, depending on a relationship between a frequency of the input signal and a sampling rate.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Peak Detection / Multi Scale / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 400, RECONF2015-82, pp. 179-184, Jan. 2016.
Paper # RECONF2015-82 
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-100 CPSY2015-132 RECONF2015-82

Conference Information
Committee VLD CPSY RECONF IPSJ-SLDM IPSJ-ARC  
Conference Date 2016-01-19 - 2016-01-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2016-01-VLD-CPSY-RECONF-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA Implementation of a Peak Detection System using AMPD Algorithm 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Peak Detection  
Keyword(3) Multi Scale  
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1st Author's Name Fumihiko Iwasaki  
1st Author's Affiliation Nagasaki University (Nagasaki Univ)
2nd Author's Name Yuichiro Shibata  
2nd Author's Affiliation Nagasaki University (Nagasaki Univ)
3rd Author's Name Kiyoshi Oguri  
3rd Author's Affiliation Nagasaki University (Nagasaki Univ)
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Speaker Author-1 
Date Time 2016-01-21 09:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2015-100, CPSY2015-132, RECONF2015-82 
Volume (vol) vol.115 
Number (no) no.398(VLD), no.399(CPSY), no.400(RECONF) 
Page pp.179-184 
#Pages
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 


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