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Paper Abstract and Keywords
Presentation 2015-12-18 13:55
Evaluation of authenticated encryptions implemented on FPGA with high-level synthesis
Makoto Kotegawa, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) ISEC2015-55
Abstract (in Japanese) (See Japanese page) 
(in English) Competition for Authenticated Encryption Security, Applicability, and Robustness (CAESAR) which is a development and evaluation of new authenticated encryption, is carried out.
29 algorithms are evaluated software, hardware, and security.
In this paper, we classify CAESAR candidates using AES, on the stand point of Nonce Based and Nonce-misuse Resistance, and made hardware implementations of 4 CAESAR candidate algorithms (AES-OTR, AES-COPA, POET, SILC).
We used Xilinx Zynq XC702 Evaluation Board and High Level Synthesis (HLS) for designing circuit.
As a result, AES-OTR shows the best performance in processing speed, and SILC in implementation area.
Keyword (in Japanese) (See Japanese page) 
(in English) AES-OTR / AES-COPA / authenticated encryption / CAESAR / high level synthesis / POET / SILC / ZYNQ-7000  
Reference Info. IEICE Tech. Rep., vol. 115, no. 376, ISEC2015-55, pp. 9-16, Dec. 2015.
Paper # ISEC2015-55 
Date of Issue 2015-12-11 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ISEC  
Conference Date 2015-12-18 - 2015-12-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2015-12-ISEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of authenticated encryptions implemented on FPGA with high-level synthesis 
Sub Title (in English)  
Keyword(1) AES-OTR  
Keyword(2) AES-COPA  
Keyword(3) authenticated encryption  
Keyword(4) CAESAR  
Keyword(5) high level synthesis  
Keyword(6) POET  
Keyword(7) SILC  
Keyword(8) ZYNQ-7000  
1st Author's Name Makoto Kotegawa  
1st Author's Affiliation National Defense Academy (NDA)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy (NDA)
3rd Author's Name Hidema Tanaka  
3rd Author's Affiliation National Defense Academy (NDA)
4th Author's Name Takakazu Kurokawa  
4th Author's Affiliation National Defense Academy (NDA)
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Speaker Author-1 
Date Time 2015-12-18 13:55:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2015-55 
Volume (vol) vol.115 
Number (no) no.376 
Page pp.9-16 
#Pages
Date of Issue 2015-12-11 (ISEC) 


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