Paper Abstract and Keywords |
Presentation |
2015-12-17 16:00
[Poster Presentation]
Bit-Error Analysis in TLC NAND flash memories. Yoshiaki Deguchi, Tsukasa Tokutomi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2015-75 CPSY2015-88 Link to ES Tech. Rep. Archives: ICD2015-75 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The capacity of NAND flash memory can be expanded by increasing the bit density. In particular, 3-bit/cell triple-level cell (TLC) NAND flash has extremely high capacity, whereas the reliability is degraded drastically due to the narrower read margins. NAND flash memory can store the data by injecting electrons into the floating-gate. However, traps, which may capture electrons, are generated in the tunneling oxide as the write/erase cycle increases. As a result, electrons are ejected from the floating-gate via traps in tunneling oxide. This paper analyzes bit-errors of TLC NAND flash memory when write/erase cycle is increased. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
solid-state-drive / NAND flash memory / Reliability / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 373, ICD2015-75, pp. 49-49, Dec. 2015. |
Paper # |
ICD2015-75 |
Date of Issue |
2015-12-10 (ICD, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2015-75 CPSY2015-88 Link to ES Tech. Rep. Archives: ICD2015-75 |
Conference Information |
Committee |
ICD CPSY |
Conference Date |
2015-12-17 - 2015-12-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyoto Institute of Technology |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2015-12-ICD-CPSY |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Bit-Error Analysis in TLC NAND flash memories. |
Sub Title (in English) |
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Keyword(1) |
solid-state-drive |
Keyword(2) |
NAND flash memory |
Keyword(3) |
Reliability |
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1st Author's Name |
Yoshiaki Deguchi |
1st Author's Affiliation |
Chuo University (Chuo Univ.) |
2nd Author's Name |
Tsukasa Tokutomi |
2nd Author's Affiliation |
Chuo University (Chuo Univ.) |
3rd Author's Name |
Atsuro Kobayashi |
3rd Author's Affiliation |
Chuo University (Chuo Univ.) |
4th Author's Name |
Ken Takeuchi |
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Chuo University (Chuo Univ.) |
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Speaker |
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Date Time |
2015-12-17 16:00:00 |
Presentation Time |
100 minutes |
Registration for |
ICD |
Paper # |
ICD2015-75, CPSY2015-88 |
Volume (vol) |
vol.115 |
Number (no) |
no.373(ICD), no.374(CPSY) |
Page |
p.49 |
#Pages |
1 |
Date of Issue |
2015-12-10 (ICD, CPSY) |
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