Paper Abstract and Keywords |
Presentation |
2015-12-14 11:30
Memory Application of Ultrafine FET utilizing Supramolecular Protein Takahiko Ban, Mutsunori Uenuma (NAIST), Shinji Migita (AIST), Yasuaki Ishikawa, Ichiro Yamashita, Yukiharu Uraoka (NAIST) EID2015-11 SDM2015-94 Link to ES Tech. Rep. Archives: EID2015-11 SDM2015-94 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm is fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Baio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Bio Nano Process / Junctionless-FET / Nano-particle / Memory / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 362, EID2015-11, pp. 9-12, Dec. 2015. |
Paper # |
EID2015-11 |
Date of Issue |
2015-12-07 (EID, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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EID2015-11 SDM2015-94 Link to ES Tech. Rep. Archives: EID2015-11 SDM2015-94 |
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