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Paper Abstract and Keywords
Presentation 2015-12-03 15:00
A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably.
However, there are two potential problems.
First, high energy is required in writing data to a non-volatile memory.
Secondly, write-endurance of non-volatile memories is low.
Bit-level write-reduction methods solve the above problems but their encoders/decoders' area are too much large.
In this paper, we propose an area-aware bit-level write-reduction code generation algorithm to solve the above problems.
We also propose an evaluation system to generate small-sized encoders.
Experimental results confirm the efficiency of our encoder design.
Keyword (in Japanese) (See Japanese page) 
(in English) Non-volatile memory / Writing-reduction code / Encoding/decoding / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-76, pp. 249-253, Dec. 2015.
Paper # VLD2015-76 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories 
Sub Title (in English)  
Keyword(1) Non-volatile memory  
Keyword(2) Writing-reduction code  
Keyword(3) Encoding/decoding  
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1st Author's Name Masashi Tawada  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Shinji Kimura  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Nozomu Togawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker
Date Time 2015-12-03 15:00:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-76,IEICE-DC2015-72 
Volume (vol) IEICE-115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.249-253 
#Pages IEICE-5 
Date of Issue IEICE-VLD-2015-11-24,IEICE-DC-2015-11-24 


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