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Paper Abstract and Keywords
Presentation 2015-12-03 14:10
Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement
Junya Goto, Nagisa Ishiura (K.G.)
Abstract (in Japanese) (See Japanese page) 
(in English) This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic blocks of a given program. The addresses of the basic blocks are adjusted by a unit smaller than the cache block size. A combination of the offsets that minimizes cache miss counts, which are computed by cache simulation, is searched. Since exhaustive search would require time exponential to the number of the offsets, the solution is searched by simulated annealing. An experiment on 7 benchmarks, assuming a single-level direct-mapping instruction cache, resulted in about 10% reduction in the cache miss count on average.
Keyword (in Japanese) (See Japanese page) 
(in English) cache memory / simulated annealing / offset / cache miss rate / basic block / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-74, pp. 237-241, Dec. 2015.
Paper # VLD2015-74 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement 
Sub Title (in English)  
Keyword(1) cache memory  
Keyword(2) simulated annealing  
Keyword(3) offset  
Keyword(4) cache miss rate  
Keyword(5) basic block  
1st Author's Name Junya Goto  
1st Author's Affiliation KWANSEI GAKUIN University (K.G.)
2nd Author's Name Nagisa Ishiura  
2nd Author's Affiliation KWANSEI GAKUIN University (K.G.)
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Date Time 2015-12-03 14:10:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-74,IEICE-DC2015-70 
Volume (vol) IEICE-115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.237-241 
#Pages IEICE-5 
Date of Issue IEICE-VLD-2015-11-24,IEICE-DC-2015-11-24 

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