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Paper Abstract and Keywords
Presentation 2015-12-03 12:05
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II
Yusuke Hatori, Kohei Osawa (Keio Univ.), Keigo Mizotani (Nintendo), Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Recent embedded real-time systems have required multiprocessors to achieve not only real-time con-
straints but also high throughput. In addition, the speed up of task by parallel and distributed processing is an
important problem. In our previous work, we proposed Responsive Task, which is a low latency real-time task on
Dependable Responsive Multithreaded Processor I (D-RMTP I). Responsive Task is a high-priority hard real-time
task to occupy one logical core with the interrupt wake-up structure on D-RMTP I and can be executed with dozens
of μs periods. However, Responsive Task does not support parallel and distributed processing. In this paper, we
propose Parallel Responsive Task, which supports parallel and distributed processing with Responsive Task on De-
pendable Responsive Multithreaded Processor II (D-RMTP II). We evaluate the latency between the release and
arrival time of Parallel Responsive Task when Parallel Responsive Task is executed on one core and two cores in
D-RMTP II, respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded Real-Time Systems / Multiprocessor / Simultaneous Multithreading / Real-Time OS / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 342, CPSY2015-75, pp. 81-86, Dec. 2015.
Paper # CPSY2015-75 
Date of Issue 2015-11-24 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor II 
Sub Title (in English)  
Keyword(1) Embedded Real-Time Systems  
Keyword(2) Multiprocessor  
Keyword(3) Simultaneous Multithreading  
Keyword(4) Real-Time OS  
1st Author's Name Yusuke Hatori  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Kohei Osawa  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Keigo Mizotani  
3rd Author's Affiliation Nintendo Co., Ltd. (Nintendo)
4th Author's Name Hiroyuki Chishiro  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Nobuyuki Yamasaki  
5th Author's Affiliation Keio University (Keio Univ.)
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Date Time 2015-12-03 12:05:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2015-75 
Volume (vol) IEICE-115 
Number (no) no.342 
Page pp.81-86 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2015-11-24 

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