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| Presentation | 2015-12-03 13:45 Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)  VLD2015-67 DC2015-63 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequency. On the other hand, asynchronous circuits independently perform only when and where they are needed thanks to preparing timing signals per each element. As a result, they can achieve low power consumption and high dependability. In this research, asynchronous adder circuits and synchronous adder circuits are designed and compared using the 28nm process technology. Then, the advantages of asynchronous circuits under low-voltage environments are quantitatively evaluated by measurement of signal waves and shmoo plots. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | QDImodel / HSPICE / shmooplot / asynchronous / synchronous / VLSI / C-element / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 338, VLD2015-67, pp. 189-194, Dec. 2015. | |
| Paper # | VLD2015-67 | |
| Date of Issue | 2015-11-24 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-67 DC2015-63 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2015-12-01 - 2015-12-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI |
| Sub Title (in English) | |
| Keyword(1) | QDImodel |
| Keyword(2) | HSPICE |
| Keyword(3) | shmooplot |
| Keyword(4) | asynchronous |
| Keyword(5) | synchronous |
| Keyword(6) | VLSI |
| Keyword(7) | C-element |
| Keyword(8) | |
| 1st Author's Name | Ryuhei Tachika |
| 1st Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
| 2nd Author's Name | Atsushi Kurokawa |
| 2nd Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
| 3rd Author's Name | Masashi Imai |
| 3rd Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-12-03 13:45:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-67, DC2015-63 |
| Volume (vol) | vol.115 |
| Number (no) | no.338(VLD), no.339(DC) |
| Page | pp.189-194 |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |
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