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Paper Abstract and Keywords
Presentation 2015-12-03 09:20
A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56
Abstract (in Japanese) (See Japanese page) 
(in English) This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchronous systems.For a data-flow graph~(DFG) given as an input to HLS, scheduling which orders independent operations affects not only the concurrency of operations, i.e., shareability of operational units performing those operations, but also delay due to handshake that controls the start/completion of each operation. It is important to consider the whole circuit delay, i.e., latency, including handshake-delay in scheduling because it is not negligible compared with operation-delay. On the other hand, in operation chaining which is known as a technique to reduce latency, handshakes for the operations in an operation-chain are lumped together and it leads to reduce handshake-delay. It is, therefore, also important to take operation chaining into account in scheduling. On the basis of the above discussion, a heuristic algorithm is proposed
to solve the latency minimization problem under resource constraints in terms of the number of operational units while considering operation chaining. Several results are shown by applying the proposed algorithm to a benchmark DFG.
Keyword (in Japanese) (See Japanese page) 
(in English) Four-phase dual-rail asynchronous circuit / high-level synthesis / scheduling / handshake-delay / operation chaining / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 339, DC2015-56, pp. 147-152, Dec. 2015.
Paper # DC2015-56 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-60 DC2015-56

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems 
Sub Title (in English)  
Keyword(1) Four-phase dual-rail asynchronous circuit  
Keyword(2) high-level synthesis  
Keyword(3) scheduling  
Keyword(4) handshake-delay  
Keyword(5) operation chaining  
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1st Author's Name Kohta Itani  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Tsuyoshi Iwagaki  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Hideyuki Ichihara  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tomoo Inoue  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2015-12-03 09:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2015-60, DC2015-56 
Volume (vol) vol.115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.147-152 
#Pages
Date of Issue 2015-11-24 (VLD, DC) 


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