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Paper Abstract and Keywords
Presentation 2015-12-03 10:10
An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST)
Abstract (in Japanese) (See Japanese page) 
(in English) As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VLSIs. Concerning the tolerability against multiple component error caused by a single soft-error in our design, we use the combination of comparison-retry mechanism and vote mechanism to realize on-line error correction. Under the assumption that a single soft-error does not affect beyond a certain spatial range, we consider the adjacency constraint between components in datapath. By introducing the adjacency constraint, the chance of speculative resource sharing can be increased, 3 triplicated computation algorithms can be executed in parallel, and as a result, total schedule length can be improved. The experimental result revealed that our approach can reduce the latency in many applications compared with conventional methods.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft-Error / Fault Tolerance / Component Adjacency Constraint / High-Level Synthesis / Triple Algorithm Redundancy / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-62, pp. 159-164, Dec. 2015.
Paper # VLD2015-62 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components 
Sub Title (in English)  
Keyword(1) Soft-Error  
Keyword(2) Fault Tolerance  
Keyword(3) Component Adjacency Constraint  
Keyword(4) High-Level Synthesis  
Keyword(5) Triple Algorithm Redundancy  
1st Author's Name Junghoon Oh  
1st Author's Affiliation Japan Advanced Institute Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute Science and Technology (JAIST)
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Date Time 2015-12-03 10:10:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-62,IEICE-DC2015-58 
Volume (vol) IEICE-115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.159-164 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-11-24,IEICE-DC-2015-11-24 

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