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Paper Abstract and Keywords
Presentation 2015-12-03 12:05
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) The propagation delay and the transition probability along each path inside an LSI widely vary depending on input data, and this property can be exploited to design high-performance approximation circuit with a negligible error rate.
In order to identify cones to be optimized based on input data, for a target circuit, our proposed algorithm virtually varies the operating clock frequency and simulates its behavior by incorporating timing error prediction circuits into it.
This simulation can be run at a fast speed and applied in a wide range of situations.
For the implementation and evaluation of our algorithm, we construct a novel design flow which identifies cones to be optimized on FPGA and then optimizes them by using a commercially available design tool.
In this paper, our algorithm is applied to ISCAS85 benchmarks.
Experimental results show that our algorithm can achieve performance increase by up to 16.7% within acceptable error rate of 2.1% compared with conventional design techniques.
These results also show that the efficiency of our algorithm varies depending on input data.
Keyword (in Japanese) (See Japanese page) 
(in English) approximation circuit design / input data dependent / timing error prediction circuit / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-66, pp. 183-188, Dec. 2015.
Paper # VLD2015-66 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA 
Sub Title (in English)  
Keyword(1) approximation circuit design  
Keyword(2) input data dependent  
Keyword(3) timing error prediction circuit  
Keyword(4) FPGA  
1st Author's Name Kazushi Kawamura  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Date Time 2015-12-03 12:05:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-66,IEICE-DC2015-62 
Volume (vol) IEICE-115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.183-188 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-11-24,IEICE-DC-2015-11-24 

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