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Paper Abstract and Keywords
Presentation 2015-12-03 10:50
Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment
Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory.
But the cache occupies a large part of the processor energy consumption. Furthermore, due to SRAM characteristic, cache cannot reduce supply voltage compared to CPU core so that DVFS cannot reduce much cache energy. So, we thought that we can reduce further cache energy consumption by preparing different power and speed design cache and switches them in proportion to DVFS activity.
Our proposal reduces energy by modifying cache hierarchy to prioritizing low-power and low-speed cache in proportion to DVFS activity.
Keyword (in Japanese) (See Japanese page) 
(in English) Cache Energy Consumption Reduction / DVFS / Cache Memory / L1 High Power/Low Power Cache / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 342, CPSY2015-72, pp. 63-68, Dec. 2015.
Paper # CPSY2015-72 
Date of Issue 2015-11-24 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment 
Sub Title (in English)  
Keyword(1) Cache Energy Consumption Reduction  
Keyword(2) DVFS  
Keyword(3) Cache Memory  
Keyword(4) L1 High Power/Low Power Cache  
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1st Author's Name Kaoru Saito  
1st Author's Affiliation Toyohashi University of Technology (Toyohashi Univ of Tech)
2nd Author's Name Ryotaro Kobayashi  
2nd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ of Tech)
3rd Author's Name Hajime Shimada  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
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Speaker
Date Time 2015-12-03 10:50:00 
Presentation Time 25 
Registration for CPSY 
Paper # IEICE-CPSY2015-72 
Volume (vol) IEICE-115 
Number (no) no.342 
Page pp.63-68 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2015-11-24 


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