Paper Abstract and Keywords |
Presentation |
2015-12-02 15:55
A low-power soft error tolerant latch scheme on 15nm process Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.) VLD2015-56 DC2015-52 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever before.
In literature, several soft error tolerant techniques have been proposed.
However due to the power constraints, new techniques for high-tolerant and low-power are needed.
In this paper, we propose a New-SEH latch design, and implement it in NCSU 15nm technology.
The simulation results show that the proposed latch obtains up to 84.39$%$ power reduction compared to SEH latch. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Power / Soft Error Hardened (SEH) Latch / Soft error / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 338, VLD2015-56, pp. 123-127, Dec. 2015. |
Paper # |
VLD2015-56 |
Date of Issue |
2015-11-24 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2015-56 DC2015-52 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A low-power soft error tolerant latch scheme on 15nm process |
Sub Title (in English) |
|
Keyword(1) |
Power |
Keyword(2) |
Soft Error Hardened (SEH) Latch |
Keyword(3) |
Soft error |
Keyword(4) |
|
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Saki Tajima |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Youhua Shi |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Masao Yanagisawa |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
|
5th Author's Affiliation |
() |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2015-12-02 15:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-56, DC2015-52 |
Volume (vol) |
vol.115 |
Number (no) |
no.338(VLD), no.339(DC) |
Page |
pp.123-127 |
#Pages |
5 |
Date of Issue |
2015-11-24 (VLD, DC) |
|