Paper Abstract and Keywords |
Presentation |
2015-12-02 14:10
A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique Norihito Tohge, Tetsuya Iizuka, Toru Nakura (Univ. of Tokyo), Satoshi Miura, Yoshimichi Murakami (THine), Kunihiro Asada (Univ. of Tokyo) CPM2015-130 ICD2015-55 Link to ES Tech. Rep. Archives: CPM2015-130 ICD2015-55 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A quick-lock all-digital Clock-Data Recovery circuit that does not require a reference clock is propposed. Internal
Time-to-Digital Converter and Phase Selector share a set of inverter-based delay lines and that enables quick frequency locking
by using few bits of preamble signal. This CDR circuit is composed of standard-cell-based digital circuit and does not consume
dynamic power in its stand-by phase. Therefore, the proposed circuit is suitable especially for Internet-of-Everything applications
that work intemittently and demand small power consumption. In this design, newly-proposed fractional-phase-selection
technique is introduced to ameliorate its jitter tolerance. A proof-of-concept design is implemented in a 65 nm FD-SOI process
and verified by simulations. The circuit works from 1.2 to 2.3 Gbps and consumes 22.3mW at 2.3 Gbps while occupying
0.21mm2. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Clock-Data Recovery / Burst-Mode CDR / Refelence-Less / All-Digital / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 341, ICD2015-55, pp. 17-22, Dec. 2015. |
Paper # |
ICD2015-55 |
Date of Issue |
2015-11-24 (CPM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
CPM2015-130 ICD2015-55 Link to ES Tech. Rep. Archives: CPM2015-130 ICD2015-55 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
ICD |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Design of a Quick-Lock All-Digital CDR with Improved Jitter Performance by Fractional Phase Selection Technique |
Sub Title (in English) |
|
Keyword(1) |
Clock-Data Recovery |
Keyword(2) |
Burst-Mode CDR |
Keyword(3) |
Refelence-Less |
Keyword(4) |
All-Digital |
Keyword(5) |
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Keyword(6) |
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Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Norihito Tohge |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Tetsuya Iizuka |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Toru Nakura |
3rd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
4th Author's Name |
Satoshi Miura |
4th Author's Affiliation |
THine Electronics, Inc. (THine) |
5th Author's Name |
Yoshimichi Murakami |
5th Author's Affiliation |
THine Electronics, Inc. (THine) |
6th Author's Name |
Kunihiro Asada |
6th Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2015-12-02 14:10:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
CPM2015-130, ICD2015-55 |
Volume (vol) |
vol.115 |
Number (no) |
no.340(CPM), no.341(ICD) |
Page |
pp.17-22 |
#Pages |
6 |
Date of Issue |
2015-11-24 (CPM, ICD) |
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