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| Presentation | 2015-12-02 16:20 Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)  VLD2015-57 DC2015-53 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG). This technique controls Power Switch (PS) by leakage monitor circuit. This technique enables us to reduce energy overhead due to sleep control circuit and realize efficient power gating depending on temperature. We evaluated leakage energy dissipation by using simulation for microprocessor which applied FGPG. The impact of process variations is also discussed. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Fine-Grain Power Gating / Leakage Monitor / Low Power / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 338, VLD2015-57, pp. 129-134, Dec. 2015. | |
| Paper # | VLD2015-57 | |
| Date of Issue | 2015-11-24 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-57 DC2015-53 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2015-12-01 - 2015-12-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating |
| Sub Title (in English) | |
| Keyword(1) | Fine-Grain Power Gating |
| Keyword(2) | Leakage Monitor |
| Keyword(3) | Low Power |
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| 1st Author's Name | Masaru Kudo |
| 1st Author's Affiliation | Shibaura Institute of Technology (Shibaura Institute of Tech.) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology (Shibaura Institute of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2015-12-02 16:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-57, DC2015-53 |
| Volume (vol) | vol.115 |
| Number (no) | no.338(VLD), no.339(DC) |
| Page | pp.129-134 |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |
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