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Paper Abstract and Keywords
Presentation 2015-12-02 17:10
The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit
Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP) Link to ES Tech. Rep. Archives: CPM2015-134 ICD2015-59
Abstract (in Japanese) (See Japanese page) 
(in English) The leakage has been increasing by miniaturization of the transistor in recently year. Adaptive body bias generator with controlled threshold voltage and leakage current using 65nm SOTB (Silicon on Thin Buried oxide) CMOS process is present this paper. Using this propose circuit, the power consumption at the minimum operating point of the logic circuit was obtained by simulation to be reduced by up to 43.8%. In measurement, it was confirmed that it outputs a constant voltage in the power supply voltage 0.5V or more.
Keyword (in Japanese) (See Japanese page) 
(in English) Body bias / Ultra-low power / SOTB process cmos / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 341, ICD2015-59, pp. 39-43, Dec. 2015.
Paper # ICD2015-59 
Date of Issue 2015-11-24 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To ICD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit 
Sub Title (in English)  
Keyword(1) Body bias  
Keyword(2) Ultra-low power  
Keyword(3) SOTB process cmos  
1st Author's Name Tomoaki Koide  
1st Author's Affiliation The University of Electro-Communications (UEC)
2nd Author's Name Kouichirou Ishibashi  
2nd Author's Affiliation The University of Electro-Communications (UEC)
3rd Author's Name Nobuyuki Sugi  
3rd Author's Affiliation Low Power Electronics Association & Project (LEAP)
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Date Time 2015-12-02 17:10:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-CPM2015-134,IEICE-ICD2015-59 
Volume (vol) IEICE-115 
Number (no) no.340(CPM), no.341(ICD) 
Page pp.39-43 
#Pages IEICE-5 
Date of Issue IEICE-CPM-2015-11-24,IEICE-ICD-2015-11-24 

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