Paper Abstract and Keywords |
Presentation |
2015-12-02 11:15
A C Framework for Integrating Algorithm Description and CGRA Implementation Yasuhiko Nakashima (NAIST) CPSY2015-65 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We need high-speed, low-cost and low-power embedded computers for intelligent IoT devices. In contrast to vector accelerators and GPGPUs that inherently require high memory bandwidth for filling SIMD facilities, accelerators based on CGRA can show good performance under severe limitations on memory bandwidth. In usual, such hardware requires special programming language and elaborate tuning to get high performance. However, many programmers need easier way to write programs with long-life language such as C and to tune the speed. In this work, an integrated programming framework that regards reusability of source code as most important is demonstrated. C codes can be compiled for both traditional computers and CGRAs, and also be used for designing hardware with high-level-synthesis. Moreover, programmers can tune CGRA programs at assembly language level just using C, and can design customized CGRA by modifying C library. As a first step, proposed CGRA description is found to show favorable performance compared with original C source code. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CGRA / C / Framework / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 342, CPSY2015-65, pp. 21-26, Dec. 2015. |
Paper # |
CPSY2015-65 |
Date of Issue |
2015-11-24 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2015-65 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
CPSY |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
Title (in English) |
A C Framework for Integrating Algorithm Description and CGRA Implementation |
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CGRA |
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Yasuhiko Nakashima |
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NARA Institute of Science and Technology (NAIST) |
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Date Time |
2015-12-02 11:15:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
CPSY2015-65 |
Volume (vol) |
vol.115 |
Number (no) |
no.342 |
Page |
pp.21-26 |
#Pages |
6 |
Date of Issue |
2015-11-24 (CPSY) |
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