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Paper Abstract and Keywords
Presentation 2015-12-01 13:10
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda (Univ. of Tokyo)
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchronous circuit, which is a kind of asynchronous circuits. High speed and tamper resistance is important in the implementation of encryption circuit. With self-synchronous circuit, it is possible to achieve high throughput by taking a dual pipeline structure. It is also difficult to predict operation from the outside by eliminating the clock so it can achieve high tamper resistance. In the operation of ECDSA, it is essential to perform modular multiplication efficiently, so we use Montgomery multiplier in this research. In Montgomery multiplier, high speed and implementation area are trade-off relation, each of which varies depending on radix. So we change the radix of the Montgomery multiplier to investigate the operation speed and implementation area. As a result of a comparison of the circuit that has been generated by the logic synthesis , the efficiency of the self-synchronous circuit is best for synchronous circuit at the radix 256bit. The area of self-synchronous circuit is about 27 times that of synchronous circuit and throughput of self-synchronous circuit is about 2 times that of the synchronous circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) self-synchronous circuit / elliptic curve cryptography / high-radix / montgomery multiplier / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 338, VLD2015-39, pp. 7-12, Dec. 2015.
Paper # VLD2015-39 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit 
Sub Title (in English)  
Keyword(1) self-synchronous circuit  
Keyword(2) elliptic curve cryptography  
Keyword(3) high-radix  
Keyword(4) montgomery multiplier  
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1st Author's Name Masato Tamura  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Makoto Ikeda  
2nd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
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Speaker
Date Time 2015-12-01 13:10:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2015-39,IEICE-DC2015-35 
Volume (vol) IEICE-115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.7-12 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2015-11-24,IEICE-DC-2015-11-24 


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