Paper Abstract and Keywords |
Presentation |
2015-12-01 13:50
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memory cell is influenced by a certain pattern of its neiborhood cells in the memory. The multi-background march test is one of test methods for NPSF, and it consists of several backgrounds and an operation sequence. However, the existing multi-background march tests are manually generated by experts to detect all NPSFs. The purpose of this paper is to reduce the test length of multi-background march test, and we present an automatic generation method of background sequence that removes redundant backgrounds by taking the relation between order of background and detected faults into account. Experimental results show that the proposed method can automatically generate the background pattern sequence for NPSF, and reaches high fault coverage under sequence length constraint. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Random access memory / Memory BIST / Neighborhood pattern sensitive fault / March test / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 339, DC2015-36, pp. 19-24, Dec. 2015. |
Paper # |
DC2015-36 |
Date of Issue |
2015-11-24 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2015-40 DC2015-36 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
DC |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories |
Sub Title (in English) |
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Keyword(1) |
Random access memory |
Keyword(2) |
Memory BIST |
Keyword(3) |
Neighborhood pattern sensitive fault |
Keyword(4) |
March test |
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1st Author's Name |
Shin'ya Ueoka |
1st Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
2nd Author's Name |
Tomokazu Yoneda |
2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
3rd Author's Name |
Yuta Yamato |
3rd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
4th Author's Name |
Michiko Inoue |
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Nara Institute of Science and Technology (NAIST) |
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Speaker |
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Date Time |
2015-12-01 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
VLD2015-40, DC2015-36 |
Volume (vol) |
vol.115 |
Number (no) |
no.338(VLD), no.339(DC) |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2015-11-24 (VLD, DC) |
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