Paper Abstract and Keywords |
Presentation |
2015-11-21 11:15
A bit serial multiply and accumulator with negative number operation Daichi Okamoto (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Yoshihiro Sejima, Yoichiro Sato, Tomoyuki Yokogawa, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2015-58 MSS2015-32 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, digital hearing aids with the high functionality of digital signal processor (DSP) become widely used, and thus its battery life is limited to only few days by a heavy load on its DSP. In order to solve this problem, we have provided a low area and power saving bit serial multiplier by using a ring oscillator. However, since the multiplier does not support the negative number operation, it cannot be applied to the multiply and accumulator used by digital filter. Therefore, we propose a multiplier capable of complement by the two's complement representation. We designed the bit serial multiply and accumulator and exhibited the simulation results that showed the intended behavior. We also showed the effectiveness of the proposed multiply and accumulator through power consumption analysis on FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
digital hearing aid / bit serial / two's complement / DSP / ring oscillator / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 315, CAS2015-58, pp. 115-120, Nov. 2015. |
Paper # |
CAS2015-58 |
Date of Issue |
2015-11-13 (CAS, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CAS2015-58 MSS2015-32 |
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