Paper Abstract and Keywords |
Presentation |
2015-10-29 16:30
[Invited Talk]
Low-power and high-speed FPGA by adjacent integration of flash memory and CMOS logic Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinichi Yasuda (Toshiba) SDM2015-75 Link to ES Tech. Rep. Archives: SDM2015-75 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Novel nonvolatile programmable switch for low-power and high-speed FPGA where flash memory is adjacently integrated to CMOS logic is demonstrated. The flash memory and high-speed switching transistor are fabricated close to each other without deteriorating their respective performance. Furthermore, programming schemes to write and erase the flash memory are optimized so that the memory is successfully programmed without any damage to the switching transistors. Flash-based configuration memory in the nonvolatile programmable switch has only half the area of the conventional SRAM-based one, and it can be placed in each block in FPGA, enabling efficient power gating that offers low-power FPGA operation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / MONOS flash memory / SONOS flash memory / Low power / Nonvolatile memory / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 280, SDM2015-75, pp. 23-28, Oct. 2015. |
Paper # |
SDM2015-75 |
Date of Issue |
2015-10-22 (SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2015-75 Link to ES Tech. Rep. Archives: SDM2015-75 |
Conference Information |
Committee |
SDM |
Conference Date |
2015-10-29 - 2015-10-30 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Niche, Tohoku Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Process Science and New Process Technology |
Paper Information |
Registration To |
SDM |
Conference Code |
2015-10-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Low-power and high-speed FPGA by adjacent integration of flash memory and CMOS logic |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
MONOS flash memory |
Keyword(3) |
SONOS flash memory |
Keyword(4) |
Low power |
Keyword(5) |
Nonvolatile memory |
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1st Author's Name |
Koichiro Zaitsu |
1st Author's Affiliation |
Toshiba Corporatiobn (Toshiba) |
2nd Author's Name |
Kosuke Tatsumura |
2nd Author's Affiliation |
Toshiba Corporatiobn (Toshiba) |
3rd Author's Name |
Mari Matsumoto |
3rd Author's Affiliation |
Toshiba Corporatiobn (Toshiba) |
4th Author's Name |
Masato Oda |
4th Author's Affiliation |
Toshiba Corporatiobn (Toshiba) |
5th Author's Name |
Shinichi Yasuda |
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Toshiba Corporatiobn (Toshiba) |
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Speaker |
Author-1 |
Date Time |
2015-10-29 16:30:00 |
Presentation Time |
50 minutes |
Registration for |
SDM |
Paper # |
SDM2015-75 |
Volume (vol) |
vol.115 |
Number (no) |
no.280 |
Page |
pp.23-28 |
#Pages |
6 |
Date of Issue |
2015-10-22 (SDM) |
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