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| Presentation | 2015-08-04 09:30 The Network-on-Chip Optimization By Using Of Genetic Algorithm Daichi Murakami, Kei Hiraki (UTokyo)  CPSY2015-16 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Hetero-NoC is a new design of Network-on-Chip (NoC) which achieves lower latency without increasing the amount of resources. In Hetero-NoC's design, two different sizes of components should be arranged properly. Previous arrangements, however, depend on the center-oriented traffic property which is seen in only simple NoC, so it is suspicious that these arrangements could benefit the real NoC which is often more complex. In addition, the method of designing Hetero-NoC from its qualitative aspects is not formalized yet and predicated to be difficult because of many factors in NoC like the location of memory controller, routing algorithm, and so on. In this research, we optimized the arrangements of the NoC's components by using of NoC simulation and genetic algorithm. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | NoC / Hetero-NoC / Genetic Algorithm / Optimization / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 174, CPSY2015-16, pp. 1-6, Aug. 2015. | |
| Paper # | CPSY2015-16 | |
| Date of Issue | 2015-07-28 (CPSY) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2015-16 |
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| Conference Information | |
| Committee | CPSY DC IPSJ-ARC |
| Conference Date | 2015-08-04 - 2015-08-06 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | B-Con Plaza (Beppu) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2015-08-CPSY-DC-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Network-on-Chip Optimization By Using Of Genetic Algorithm |
| Sub Title (in English) | |
| Keyword(1) | NoC |
| Keyword(2) | Hetero-NoC |
| Keyword(3) | Genetic Algorithm |
| Keyword(4) | Optimization |
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| 1st Author's Name | Daichi Murakami |
| 1st Author's Affiliation | The University of Tokyo (UTokyo) |
| 2nd Author's Name | Kei Hiraki |
| 2nd Author's Affiliation | The University of Tokyo (UTokyo) |
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| Speaker | Author-1 |
| Date Time | 2015-08-04 09:30:00 |
| Presentation Time | 30 minutes |
| Registration for | CPSY |
| Paper # | CPSY2015-16 |
| Volume (vol) | vol.115 |
| Number (no) | no.174 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2015-07-28 (CPSY) |
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