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| Presentation | 2015-06-19 12:00 An Area Optimization of 3D FPGA with high speed inter-layer communication link Yuto Takeuchi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ)  RECONF2015-4 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Three-dimensional (3D) stacking technology is attractive for providing another way to improve the performance of the large scale integration (LSI) rather than miniaturization. However, because the through-silicon-via (TSV) of the vertical connection has a large area overhead, it is necessary to reduce the quantity of vertical routing resources that heavily required by the field-programmable gate array (FPGA). In this paper, we first create a face-down stacked FPGA by dividing routing and logic resources into different layers. Then, in order to minimize the number of TSVs and improve integration, face-down stacked FPGAs are connected by high speed serial links. The evaluation on the proposed 3D FPGA is performed with an area-minimized circuit partitioning method. Results show that a four layers 3D FPGA has a 10.78% slower delay while 70.21% smaller area than a 2D FPGA on average. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | 3D-FPGA / High speed serial communication / TSV / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 109, RECONF2015-4, pp. 17-22, June 2015. | |
| Paper # | RECONF2015-4 | |
| Date of Issue | 2015-06-12 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2015-4 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2015-06-19 - 2015-06-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyoto University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2015-06-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Area Optimization of 3D FPGA with high speed inter-layer communication link |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | High speed serial communication |
| Keyword(3) | TSV |
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| 1st Author's Name | Yuto Takeuchi |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 2nd Author's Name | Qian Zhao |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 5th Author's Name | Morihiro Kuga |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
| 6th Author's Name | Toshinori Sueyoshi |
| 6th Author's Affiliation | Kumamoto University (Kumamoto Univ) |
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| Speaker | Author-1 |
| Date Time | 2015-06-19 12:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2015-4 |
| Volume (vol) | vol.115 |
| Number (no) | no.109 |
| Page | pp.17-22 |
| #Pages | 6 |
| Date of Issue | 2015-06-12 (RECONF) |
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