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| Presentation | 2015-06-19 13:40 Fabrication of PtGe/Ge contacts with low hole barrier and its application to metal source/drain Ge p-channel MOSFETs Yuta Nagatomi, Shintaro Tanaka, Yuichi Nagaoka, Keisuke Yamamoto, Dong Wang, Hiroshi Nakashima (Kyushu Univ.)  SDM2015-47 Link to ES Tech. Rep. Archives: SDM2015-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The fabrication of PtGe/Ge contacts with low hole barrier height (ΦBP) and its electrical passivation were investigated. A PtGe/n-Ge contact passivated by an ultrathin SiO2/GeO2 bilayer showed a high electron barrier height of 0.64 eV, indicating ΦBP~0 eV and an on/off ratio of ~106. A p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness of 3.4 nm was fabricated using PtGe contacts as the source/drain (S/D), which showed well-behaved transistor operation. By investigating device performance, we showed that the on/off ratio of drain current and the parasitic resistance of PtGe-S/D p-MOSFETs were much superior to those of HfGe-S/D p-MOSFETs. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Ge / MOSFET / metal S/D / parasitic resistance / passivation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 108, SDM2015-47, pp. 47-50, June 2015. | |
| Paper # | SDM2015-47 | |
| Date of Issue | 2015-06-12 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2015-47 Link to ES Tech. Rep. Archives: SDM2015-47 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2015-06-19 - 2015-06-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | VBL, Nagoya Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Material Science and Process Technology for MOS Devices and Memories |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2015-06-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fabrication of PtGe/Ge contacts with low hole barrier and its application to metal source/drain Ge p-channel MOSFETs |
| Sub Title (in English) | |
| Keyword(1) | Ge |
| Keyword(2) | MOSFET |
| Keyword(3) | metal S/D |
| Keyword(4) | parasitic resistance |
| Keyword(5) | passivation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuta Nagatomi |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Shintaro Tanaka |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Yuichi Nagaoka |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 4th Author's Name | Keisuke Yamamoto |
| 4th Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 5th Author's Name | Dong Wang |
| 5th Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 6th Author's Name | Hiroshi Nakashima |
| 6th Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-06-19 13:40:00 |
| Presentation Time | 20 minutes |
| Registration for | SDM |
| Paper # | SDM2015-47 |
| Volume (vol) | vol.115 |
| Number (no) | no.108 |
| Page | pp.47-50 |
| #Pages | 4 |
| Date of Issue | 2015-06-12 (SDM) |
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